Our Research
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CFET
Complementary field effect transistor (CFET) is the latest 3D structure, following the success of FinFET. CFET is formed by stacking the nFET on top of the pFET, which can successfully reduce the layout area.
For the fabrication process in our lab, we use membrane transfer to make the upper transistor instead of epitaxy. We choose hafnium oxide as high-k material and titanium nitride as gate metal. Hafnium oxide and titanium nitride wrap around silicon channels conformally by ALD, successfully achieving gate-all-around stacked nanosheet structure.
Besides, our lab is working on germanium/silicon heterogeneous CFET 3D SRAM simulation. We will complete germanium/silicon heterogeneous device in the future.
3D schematic for 6T SRAM
CFET 6T SRAM
高效能三維SRAM架構
2D schematic for 6T SRAM
TEM cross section
Membrane transfer
Low Bandgap Semiconductor
Low Bandgap semiconductor has drawn a significant attention because of its swift switching capability and infrared application. Our focus in this field is to utilize a novel semiconductor material with tunable bandgap to achieve mid-IR absorption and emission device for future communication usage.
We engineer wafer-scale thin-film low bandgap semiconductor (thickness<100nm) and combine it with advanced nano-structuture and nano-optics technique. We demonstrate that great potential in mid-IR field can be achieved if multiple-discipline techniques can be integrated.
Direct transfer of large-area GeSn from Si substrate
Packaging of 3DIC
The effective dispersion of 2D materials with superior planar phonon scattering characteristic in polymer can yield plastic materials with metal like thermal conductivity. This enables the new era in packaging the chip as thermal management dominates the compact 3DIC designs. In short, we make the plastic as thermal conductive as metal.
Our goals focus on engineering the next generation chip packaging materials that can enable the breakthrough performance.
Superior thermal dissipation capability
Graphene composites packaged on the chip carrier
2D Materials
Recently, many approaches have been proposed for the universal GNRs preparation with edge arranged in atomic level accuracy.
For Graphene-based logic device, GNRs are a choice to open bandgap when its width scales down to nanometers. However, the mobility of GNRs quickly declines as the width reduction of GNRs is the requirement to open the bandgap of graphene, while its original mobility up to 2E5 cm2/Vs. In this study, we calculate the structured GNRs and its electrical properties. Coved-Edge GNRs (CGNRs), contains zigzag and armchair edges regularly, is considered to delve into the relations between the structured edges and phonon and then analyzed through the electron-phonon interaction.
We show that this special lattice structure if developed in the future engineering procedure can be helpful to enhance GNRs with good transport characteristics even when the width of GNRs are short and electrons is under highly quantum-confinement.
